• Intel Corporation, Platform Support for IEEE 754R Decimal Floating-Point Arithmetic in the Bid Format

• 7,467,174 - Processing unit having decimal floating-point divider using Newton-Raphson iteration, granted Dec 2008.
• 6,912,559 - System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit, granted Jun 2005.

• "Instruction set extensions for software defined radio"

Mamidi S, Blem E, Schulte MJ, et al., Microprocessors and Microsystems 33 (4): 260-272 Jun 2009. The authors present instruction set extensions for several important communication algorithms including cyclic redundancy checking, convolutional encoding. Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding.

• "A low-power multithreaded processor for software defined radio"

Schulte M, Glossner J, Jinturkar S, et al., Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 43 (2-3): 143-159 Jun 2006. Architectures, Modeling, and Simulation for Embedded Processor. In this paper, the authors present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption.

• "Dual-mode floating-point multiplier architectures with parallel operations"

Akkas A, Schulte MJ, Journal of Systems Architecture 52 (10): 549-562 Oct 2006. This paper presents the architecture of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications.

• "Integer multipliers with overflow detection"

Gok M, Schulte MJ, Arnold MG, IEEE Transactions on Computers 55 (8): 1062-1066 Aug 2006. This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands.

• Madison Embedded Systems and Architectures Laboratory
• Agere Systems, Lehigh Valley Central Campus, Kent E. Wires
• Cukorova University, Mustafa Gok
• Lehigh University
• Koc University, Ahmet Akkas
• IBM, Server and Technology group, Mark A. Erle

Technical Advisory Board Member/Principal Consultant, Sandbridge Technologies